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30Gbits Parallel Optical Receiver Module


第 27 卷   4 期 第 2006 年 4 月

半        导 体 学 报
C H IN ESE J OU RNAL O F SEMICONDUC TORS

Vol. 27   . 4 No Ap r. ,2006

1  Introduction

Wave divisio n multiplexing ( WDM ) and time divisio n multiplexing ( TDM ) are t wo important technologies in modern op tical co mmunicatio n sys2 tems. To support t hese multiplexing systems ,high2 speed devices and devices wit h accurate wave2 lengt hs and limited bands , such as LDs , modula2 tor s , PDs , and wave2divided guides and de2multi2 plexers must be developed and p ro duced. The high co st of t hese devices is acceptable fo r lo ng distance co mmunicatio n , but in short2 or very2short2reach co mmunicatio n systems , WDM and TDM architec2 t ures are too expensive. A parallel optical co mmunicatio n system a2 dopt s more t han o ne fiber to t ransmit signal s. U n2 like WDM and TDM , it adopt s low or medium speed t ransmit ter s and receiver s. By simply repeat 2 ing t hese p hysical co nveyance channel s , o ne can easily o btain a communication system with a trans2 mitting ability that exceeds tens of Gbit/ s[ 1 ,2 ] . In what are called V SR ( very2short2reach ) systems , t he scheme of adop ting more fiber channel s is co st ef 2 fective. It is wort h using parallel optical co mmuni2 catio n to realize high2speed t ransmissio n. Because
Cor resp ondi ng aut hor . Email :p eiw h @red. se mi . ac . c n

 Received 30 Dece mber 2005 , revised ma nuscrip t received 4 Februa ry 2006

3 Pr oject supp ort ed by t he National High Tec h nology Resea rc h a nd Develop me nt Pr ogra m of Chi na ( N os . 2003 AA 302240 , 2003 AA 312040 )
a nd t he National Nat ural Scie nce Foundation of Chi na ( N os . 30300378 , 60536030 , 60502005)

Abstract : A 30 Gbit/ s recep t or module is develop e d wit h a CMOS i ntegrated receive r chip ( I C) a nd a GaAs2based 1 × p h ot o detect or a r ray of PIN2t yp e . Pa rallel tech nology is a dop ted i n t his module t o realize a high2sp ee d re2 12 ceive r module wit h me dium sp ee d devices . A high2sp eed p ri nte d circuit boar d ( PCB ) is designe d a nd p r oduced. The I C chip a nd t he PD a r ray a re p ac kaged on t he PCB by c hip2on2boar d tech nology. Flip c hip alignme nt is use d f or t he PD a r ray accurately asse mbled on t he module s o t hat a p lug2t yp e op tical p ort is built . Test results s how t hat t he module ca n receive p a rallel signals at 30 Gbit/ s . The se nsitivit y of t he module is - 131 6 dB m f or 10 - 13 B ER . Key words : receive r module ; p a rallel ; PD a r ray PACC : 4280L ; 4282    EEACC : 6260 CLC number : TN 36     Document code : A     Article ID : 025324177 ( 2006) 0420696204

30 Gbit/ s Parallel Optical Receiver Module 3
Chen Hongda , Jia Jiuchun , Pei Weihua , and Tang J un
Chi nese A ca dem y of S ciences , B ei j i n g   100083 , Chi na) ( S t ate Key L aboratory of I nte g rated O ptoelect ronics , I nstit ute of S emicon d uctors ,

of t he advantage in co st ,of t he five suggestio ns for V SR criteria app roved by t he Op tical Internet 2 working Forum ( O IF ) f ro m 2000 to 2003 [ 3 ] , t hree are parallel schemes. So me key devices such as t ransmitter modules and receiver modules for par2 allel optical co mmunicatio n systems have been de2 veloped and p roduced by so me major equip ment vendor s[ 4 ,5 ] . In t his paper ,we p resent a parallel optical re2 ceiver module developed by o ur gro up . It has 12 re2 ceiver channel s working at a wavelengt h of 850nm. Each channel can work at 21 5 Gbit/ s. The net data receptio n speed over 12 channel s can achieve 30 Gbit/ s. The receiver mo dule was fabricated wit h an integrated chip ( IC ) and PIN detector array. These t wo devices were integrated and packaged by chip2o n2board technology. The elect rical and t he optical port s are designed for hot plugging.

2  High speed PIN detector array

The p hoto detector is a GaA s2based 1 ×12 PIN array. The dimensio ns of t he PD array are μ μ μ 3400 m in lengt h , 600 m in widt h , and 200 m in t hickness. The diameter of t he sensitive area is μ μ 80 m. A multimo de fiber wit h a 621 5 m core can
○ c 2006 Chi nese I nstit ute of Elect r onics

第4期

Chen Hongda et al . :   Gbit/ s Parallel Optical Receiver Module 30

697

The optical receiver integrated circuit ( IC ) was made wit h standard CMOS technology. It co n2 tains t welve amplifier channel s ,each of which co n2 tains t wo kinds of amplifiers. The fir st stage is a t rans2impedance amplifier and t he seco nd stage is a limiting amplifier. The t rans2impedance amplifier wit h an inp ut capacitance up to 600f F ( t he int rinsic capacitance of t he p hoto2detector ) achieves a - 3dB bandwidt h greater t han 21 9 GHz. The limiting am2 plifier p rovides a differential CML ( current mode

be easily aligned wit h t he PD array. The distance bet ween t he wire bo nd pads and t he sensitive area μ is extended to 500 m in order to facilitate co upling and bo nding. The average respo nsivit y of t he PDs at a wavelengt h of 850nm is 01 55W/ A . U nder a 10V rever se voltage ,t he t ypical dark current is less t han 01 01nA ,as shown in Fig. 1 ( b) . The capacitances of t he PDs are lower t han 01 5p F. The rise and fall times are less t han 80p s. The bandwidt h of t he PDs can reach 5 GHz.

3  Optical receiver IC

Fig. 1  Opto2elect ric characteristic of PD array  ( a) Relative responsivity versus wavelengt h ; ( b) I2V curves

A 1 × ribbo n fiber wit h a standard M T co n2 12 nector was used to co uple light into t he PD array , which was mo unted bet ween t wo pins o n a sub2 st rate wit h a device called a pin2holder . The t wo pins were designed to p recisely orient t he M T co n2 nector and were plugged into a pair of holes o n t he M T co nnecto r. In t his way ,light can be co upled in2 to t he PD array as lo ng as it s sensitive area is a2 ligned wit h t he ribbo n fiber ,just like a socket to a plug. Fo r t his p urpo se ,t he po sitio n of t he PD array bet ween t he t wo pins is impo rtant ,as it determines t he success of t he co upling. We designed an ap2 p roach to guarantee t hat t he PD array is placed in t he right po sitio n. First , an alignment mold wit h holes corre2 spo nding to t he pins and orientatio n markings for alignment was p recisely fabricated wit h an elect ric discharge p rocess. The PD array and t he alignment mold were t hen aligned face2to2face o n a flip chip machine. The machine can achieve an alignment μ p recisio n of 1 m. This p recisio n is high eno ugh to μ co uple a multi2fiber to an 80 m2wide sensitive are2 a. Next , t he PD array and t he mold were joined wit h solder at 150 ℃ After t hese operatio ns , t he . desired alignment was achieved. The next step was to t ransfer t he PD array f ro m t he mold to t he pin2 holder. The mold wit h t he PD array soldered to it was co nnected to t he pin2holder by inserting t he pins into t he holes. Because t he mold has t he same hole po sitio ns and p recise dimensio ns as t ho se of t he M T co nnector , t he PD array was t hen located in t he right po sitio n bet ween t he pins o n t he pin2 holder. Af ter t he PD array was fixed wit h glue ,t he mold was heated and taken off . At t his point , an optical port , which can be hot2plugged , has been finished. To co uple light into PD array , o ne can

logic) o utp ut t hat can be used to drive CML2co m2 patible data or a clock recovery circuit . The sensi2 μ tivit y of t he amplifiers can reach 8 A wit h a 10 - 12 bit error rate. This amplifier design satisfies t he sensitivit y and bit rate requirement s at 21 5 Gbit/ s. The receiver IC is supplied by a 31 3V power , which p rovides a rever se voltage for each p hoto de2 tector . To facilitate t he wire bo nding ,t he signal2in2 p ut pads o n t he IC chip are spatially arranged in t he same way as t ho se o n t he PDs.

4  Alignment of PD array

698

半        导 体 学 报

第 27 卷

simply plug a fiber ribbo n wit h an M T co nnector to t he pins ,as shown in Fig. 2.

Fig. 3   mpleted receiver module Co

5   Receiver module assembling and packaging
  Chip2o n2board ( COB ) technology is a kind of technology t hat can p rovide simple packaging fo r dies. We adopted it here to package t he receiver mo dule. Fir st , t he receiver IC was glued to t he high2speed PCB. The glue was t hen solidified by heating. Next , t he PCB wit h t he glued2o n IC and t he pin2holder wit h t he at tached PD were assem2 bled into a metallic case. The pads of t he IC and t he PD array must be adjusted to be o n t he same plane. Then , gold wire was bo nded to co nnect t he circuit in t he module. Af ter t his , special glue was injected into t he case to p rotect t he chip s and t he co nnecting wires. Finally ,t he case was covered and sealed wit h solder . An optical window was lef t o n t he cover to p rovide an access for t he ribbo n fiber wit h t he M T co nnector . A co mpleted receiver mod2 ule is shown in Fig. 3.

6  Test results

The receptivit y and characteristics of t he re2 ceiver module were tested wit h a co mmercial 1 × 12 parallel optical t ransmit ter module. Each channel of

Fig. 2   Schematic of alignment fo r PD array and 1 × 12 ribbo n fiber wit h M T connecto r  (a) 1 × ribbo n fi2 12 ber wit h M T connecto r ; ( b ) Pin2holder  ① and ②A2 lignment pins ; ③PD array ; ④Protective base ; ⑤Multi fibers ; ⑥ Alignment holes

We have developed a parallel optical receiver module wit h 12 channel s using COB technology. Bot h t he parallel elect rical port s and t he parallel optical port s support hot2plugging. The receptivit y

t he t ransmit ter can achieve 21 5bit/ s. A st ream of 223 bit s wit h p seudo2rando m sequences rate was sent at 21 5bit/ s by t he t ransmit ter into each chan2 nel . A 1 ×12 ribbo n fiber co upled t he optical sig2 nal s into t he receiver module. The elect ric o utp ut of t he receiver module was tested. Figure 4 show s a t ypical eye pat tern of o ne channel at 21 5bit/ s. The ot her channel s ’eye pat 2 terns are lit tle different f ro m t his o ne. The eye pat 2 tern indicates goo d receptivit y at 21 5bit/ s. When t he power of t he inp ut light was decreased to 131 6dB ,t he bit error rate was lower t han 10 - 13 .

7  Conclusion

Fig. 4  Typical channel eye pattern fo r 23bit PBS  (a) 11 25 Gbit/ s ; ( b) 21 5 Gbit/ s

第4期

Chen Hongda et al . :   Gbit/ s Parallel Optical Receiver Module 30

699

Acknowledgement  The aut hors acknowledge Prof . Wang Zhigo ng , Prof . Li Zhiqun ,and Mr . Xue Zha2 ofeng fo r t heir wo rk o n t he receiver IC design and t heir help wit h testing. References
[ 1 ]  Yo shihiro M , At sushi T. Optical interconnection modules uti2 lizing fiber2optic parallel t ransmission to enhance information

of t he module can reach 30 Gbit/ s when each chan2 nel is working at 21 5 Gbit/ s. The sensitivit y of t he mo dule is - 131 6dBm for 10 - 13 B ER.

( 中国科学院半导体研究所 集成光电子学国家重点实验室 , 北京   100083)

3 国家高技术研究发展计划 ( 批准号 : 2003 AA 302240 , 2003 AA 312040) 及国家自然科学基金 ( 批准号 : 30300378 , 60536030 , 60502005) 资助项目 通信作者 . Email :p eiw h @red . se mi . ac . cn   2005212230 收到 , 2006202204 定稿 ○ c 2006 中国电子学会

摘要 : 报道了一种基于 CMOS 工艺接收电路芯片和 GaAs 工艺 1 × 光电探测器阵列的 30 Gbit/ s 并行光接收模 12 块 . 该模块采用并行光通信方案 ,利用中高速光电子器件实现信号的高速传输 . 直接使用未经封装的接收电路裸片 和光探测器裸片 ,采用电路板上芯片技术封装制作模块 ,并通过倒装焊的方式实现了探测器阵列与列阵光纤的精 确对准并形成了可插拔的光接口 . 测试结果表明模块的接收能力可以达到 30 Gbit/ s. 误码率小于 10 - 13 时 , 接收模 块的灵敏度可以达到 - 131 6dBm. 关键词 : 接收模块 ; 并行 ; 探测器阵列 PACC : 4280L ; 4282    EEACC : 6260 中图分类号 : TN 36     文献标识码 : A     文章编号 : 025324177 ( 2006) 0420696204

30 Gbit/ s 并行光接收模块 3

陈弘达   贾九春   裴为华     唐 君

t hroughput . Hitachi Review ,1994 ,43 (2) :79 [2 ]  Carson R F ,Lovejoy M L ,Lear K L ,et al . Low2power ,paral2 lel p hotonic interconnections for multi2chip module applica2 tions. Proceedings of Elect ronic Co mponent s and Technology Conference ,1995 :380 [ 3 ]  Chen Hongda , Zuo Chao . Very short reach optical t ransmis2 sion technology. Beijing : Science Publishing Co mpany ,2005 :1 [ 4 ]  Simon J , Windover B L ,et al . Parallel optical interconnect at 10 Gb/ s per channel . 54t h Elect ron Co mpon and Tech Conf , 2004 :101 [ 5 ]  Fumihiko S , Hideto F , Hiroshi H ,et al . Optical parallel in2 terconnection characteristics of 42channel 22 Gbit/ s bit syn2 chronous data t ransmission module. Proceedings of Elect ronic Co mponent s Conference ,1992 :77


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